package yycore

import bus.LinkBusCmd
import chisel3._
import chisel3.util.Decoupled
import common.Constants._

class AddrReqIO extends Bundle {
  val addr = Output(UInt(AddrBits.W))
}

class DataRespIO(data_width: Int) extends Bundle {
  val data = Output(UInt(data_width.W))
}

class OnlyReadBus(data_width: Int) extends Bundle {
  val req = Decoupled(new AddrReqIO)
  val resp = Flipped(Decoupled(new DataRespIO(data_width)))
}


class DecStageCtrlBus extends Bundle {
  val rs_addr = Vec(2, Input(UInt(5.W)))
  val bypassValid = Vec(2, Output(Bool()))
  val bypass_opdata = Vec(2, Output(UInt(DataBits.W)))
}

class BRJMPIO extends Bundle {
  val exe_ctrl_pc_sel = Input(UInt(PC_4.getWidth.W))
  val fail = Input(Bool())
  val exe_br_jmp_target = Input(UInt(DataBits.W))
  val exe_jump_reg_target = Input(UInt(DataBits.W))
}

class RedirectIO extends Bundle {
  val valid = Output(Bool())
  val target = Output(UInt(AddrBits.W))
}
class ByPassDataIO extends Bundle {
  val rf_wen = Input(Bool())
  val addr = Input(UInt(5.W))
  val data = Input(UInt(DataBits.W))
  def apply(rf_wen: Bool, addr: UInt, data: UInt) = {
    this.rf_wen := rf_wen
    this.addr := addr
    this.data := data
    this
  }
}